1. Field of Invention
The present invention relates to a memory interlace-checking method, which is a test method that can detect weakened memory. Through interlacing data accesses, the method can more accurately find memory problems.
2. Related Art
Memory is an indispensable element in a computer system. It has a deterministic influence on the stability of the system. As the capacity and speed of the memory increase indefinitely, the current memory manufacturing technologies reach a scale below 0.2 micrometers, a supply voltage below 3.3 volts, and an operation speed over 133 MHz. Under such a high density, a low operation voltage and a high operation frequency, memory becomes very sensitive and is easily damaged or weakened because of the manufacturing process, external signals or noise generated inside, resulting in low stability. Therefore, how to accurately quickly detect the memory weakening problem is an important subject studied by test engineers.
According to the current state of the art in memory testing, there is a problem of being unable to accurately detect memory weakening or instability. Usual memory testing programs perform complicated state settings and data accesses through the command pins, address pins, I/O pins of the memory to detect whether each element in the memory is good or not. Taking data accessing as an example, if one wants to check the continuity of a particular word line (W/L) in the memory, the result can be obtained by employing a one-dimensional row access pattern to access the particular W/L. If one wants to check the continuity of a particular bit line (B/L) in the memory, the result can be obtained by employing a one-dimensional column access pattern to access the particular B/L. In addition, A. J. van de Goor discloses other methods such as a two-dimensional checkboard, the GALPAT, a sliding diagonal scheme and a butterfly pattern in Testing Semiconductor Memory (John Wiley & Sons, 1991) to provide better error detection effects.
Although conventional methods have many different memory testing styles, the memory address accessing, however, is more or less the same. As shown in FIG. 6A, the matrix on the left-hand side of the drawing represents the memory. Each little square refers to a memory cell. On the right-hand side is a simplified way of showing the ordering of addresses. In FIG. 6A, continuous address accessing is performed from left to right and then from top to bottom. Another method from bottom to top is employed in FIG. 6B. FIGS. 7A and 7B show the memory address accessing performed from right to left and then from top to bottom and from bottom to top, respectively. FIGS. 8A and 8B show the memory address accessing performed from top to bottom and then from left to right and from right to left, respectively. FIGS. 9A and 9B show the memory address accessing performed from bottom to top and then from left to right and from right to left, respectively. However, no matter what memory accessing scheme is taken, it is still a vertical or horizontal continuous access style (read, write or refresh). This kind of one bit by one bit access method cannot effectively detect memory weakening problems. That is, as shown in FIG. 6A, when accessing the first row from left to right, electromagnetic interference (EMI) may result in weakening in the next row. However, after finishing the access of the first row and starting the access of the second row, the second row may be strengthened from a weakened state to a normal state due to write-in, read or refresh. Therefore, the foregoing continuous memory address accessing scheme cannot effectively detect the memory weakening problems. The conventional memory test methods are neither stringent nor accurate and thus have to be improved.